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14分钟前更新
HISTORY近 30 天历史柱高表示当天去重热搜数量
507
09/08—10/07 有历史数据
  • 013986
    verilator
    Verilator open-source SystemVerilog simulator and lint systemverilator
  • 023680
    opentitan
    OpenTitan: Open source silicon root of trustlowRISC
  • 03641
    cvw
    CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.openhwfoundation
  • 041.3万
    tiny-gpu
    A minimal GPU design in Verilog to learn how GPUs work from the ground upadam-maj
  • 052081
    ibex
    Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)lowRISC